vlib work
vmap clock_generator_0_v4_03_a ../eps/simulation/behavioral/clock_generator_0_v4_03_a
vmap bram_block_mm_elaborate_v1_00_a ../eps/simulation/behavioral/bram_block_mm_elaborate_v1_00_a
#vlib ../eps/simulation/behavioral/cdn_axi4_lite_master_bfm_wrap_v2_01_a
vmap cdn_axi4_lite_master_bfm_wrap_v2_01_a ../eps/simulation/behavioral/cdn_axi4_lite_master_bfm_wrap_v2_01_a
#vlib ../eps/simulation/behavioral/cdn_axi4_master_bfm_wrap_v2_01_a
vmap cdn_axi4_master_bfm_wrap_v2_01_a ../eps/simulation/behavioral/cdn_axi4_master_bfm_wrap_v2_01_a

# my rtl
vlog -work work +define+SIM ../../rtl/InSight.v
vlog -work work ../../rtl/Switch.v
vlog -work work ../../rtl/PcieCore.v
vlog -work work ../../rtl/InternalDevice.v
vlog -work work ../../rtl/PcieBridge.v
vlog -work work ../../rtl/InternalBridge.v
vlog -work work ../../rtl/ConfigurationSpace.v
vlog -work work ../../rtl/ppb.v
vlog -work work ../../rtl/axis_router.v
vlog -work work ../../rtl/axis_pcie_dmux.v
vlog -work work ../../rtl/axis_util.v
vlog -work work ../../ipcore_dir/fwft_fifo_181.v

vsim -novopt \
  -L work -L secureip -L unisims_ver -L unimacro_ver -L xilinxcorelib_ver \
  -c glbl nvs_ex_top nvs_ex_tests nvs_ex_down_wrapper nvs_ex_up_wrapper \
  +EX_LOG +EX_RAW +EX_BASIC_GEN3_TEST +EX_USER_TEST +EX_MONITOR +EX_CHECKER +EX_TEST_DUT_UPSTREAM_PORT \
  -pli ../nsys_ex.v/lic/windows/libpli.dll \
  -pli ../cdn_axi_bfm_vip/vpi_lib/ntopt/libxil_vsim.dll
  
view wave
do wave.do
run -all
